jabara Wiki - Recent changes [en]

jabara Wiki - Recent changes [en] https://wiki.zelda.sr/wiki/Special:RecentChanges Track the most recent changes to the wiki in this feed. en MediaWiki 1.45.1 Wed, 22 Jul 2026 02:20:56 GMT Design https://wiki.zelda.sr/index.php?title=Design&diff=40&oldid=39 https://wiki.zelda.sr/index.php?title=Design&diff=40&oldid=39 <p><span class="autocomment">CPU: </span> Fix minor mistakes and inconsistencies</p> <table style="background-color: #fff; color: #202122;" data-mw="interface"> <col class="diff-marker" /> <col class="diff-content" /> <col class="diff-marker" /> <col class="diff-content" /> <tr class="diff-title" lang="en"> <td colspan="2" style="background-color: #fff; color: #202122; text-align: center;">← Older revision</td> <td colspan="2" style="background-color: #fff; color: #202122; text-align: center;">Revision as of 11:45, 13 July 2026</td> </tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l38">Line 38:</td> <td colspan="2" class="diff-lineno">Line 38:</td></tr> <tr><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>The Tegra X1 contains four [[wikipedia:ARM_Cortex-A57|ARM Cortex-A57]] cores used by the NX, as well as four unused [[wikipedia:ARM_Cortex-A53|ARM Cortex-A53]] cores. The Cortex-A57 implements the [[wikipedia:ARM_architecture_family#Armv8-A|Armv8-A]] instruction set architecture (ISA). Only its 64-bit mode ('''AArch64''') is used by HOS, so the target of jabara's CPU emulation is to emulate an AArch64 core. The instruction set used by AArch64 is known as '''A64'''.</div></td><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>The Tegra X1 contains four [[wikipedia:ARM_Cortex-A57|ARM Cortex-A57]] cores used by the NX, as well as four unused [[wikipedia:ARM_Cortex-A53|ARM Cortex-A53]] cores. The Cortex-A57 implements the [[wikipedia:ARM_architecture_family#Armv8-A|Armv8-A]] instruction set architecture (ISA). Only its 64-bit mode ('''AArch64''') is used by HOS, so the target of jabara's CPU emulation is to emulate an AArch64 core. The instruction set used by AArch64 is known as '''A64'''.</div></td></tr> <tr><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><br></td><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><br></td></tr> <tr><td class="diff-marker" data-marker="−"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>Naively, the [[wikipedia:Instruction_cycle|instruction cycle]] may be emulated to interpret A64 code on a per-instruction basis. While providing the most accurate CPU emulation, interpretation does, however, also carry drastic overhead in its slow and repetitive nature. jabara instead emulates A64 using [[wikipedia:Binary_translation#Dynamic_binary_translation|dynamic binary translation]] (DBT), in which [[wikipedia:Basic_block|basic blocks]] of A64 code are collectively translated to the ISA of the emulator ("host") machine, providing performance often better than that of the NX within basic blocks. Existing NX emulators commonly accomplish this using the [https://github.com/lioncash/dynarmic dynarmic] [[wikipedia:Dynamic_recompilation|dynamic recompiler]]. However, due to the difficulty of using [https://isocpp.org C++] libraries in Rust codebases, as well as the aforementioned issues present in <del style="font-weight: bold; text-decoration: none;">the </del>the buildsystem of yuzu that stem partially from that of dynarmic, the [http://github.com/unicorn-engine/unicorn Unicorn] CPU emulator framework, which provides [https://github.com/unicorn-engine/unicorn/tree/master/bindings/rust/unicorn-engine Rust bindings] for its underlying [https://www.c-language.org C] implementation, was chosen for jabara. Unicorn emulates various architectures, including AArch64, using [[wikipedia:Just-in-time_compilation|just-in-time compilation]] (JIT), a DBT technique also used by dynarmic that makes Unicorn a sufficiently performant framework for Tegra X1 emulation. It is based on [https://www.qemu.org QEMU], a widely-used generic machine emulator framework that achieves near-native performance in many scenarios.</div></td><td class="diff-marker" data-marker="+"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>Naively, the [[wikipedia:Instruction_cycle|instruction cycle]] may be emulated to interpret A64 code on a per-instruction basis. While providing the most accurate CPU emulation, interpretation does, however, also carry drastic overhead in its slow and repetitive nature. jabara instead emulates A64 using [[wikipedia:Binary_translation#Dynamic_binary_translation|dynamic binary translation]] (DBT), in which [[wikipedia:Basic_block|basic blocks]] of A64 code are collectively translated to the ISA of the emulator ("host") machine, providing performance often better than that of the NX within basic blocks. Existing NX emulators commonly accomplish this using the [https://github.com/lioncash/dynarmic dynarmic] [[wikipedia:Dynamic_recompilation|dynamic recompiler]]. However, due to the difficulty of using [https://isocpp.org C++] libraries in Rust codebases, as well as the aforementioned issues present in the buildsystem of yuzu that stem partially from that of dynarmic, the [http://github.com/unicorn-engine/unicorn Unicorn] CPU emulator framework, which provides [https://github.com/unicorn-engine/unicorn/tree/master/bindings/rust/unicorn-engine Rust bindings] for its underlying [https://www.c-language.org C] implementation, was chosen for jabara. Unicorn emulates various architectures, including AArch64, using [[wikipedia:Just-in-time_compilation|just-in-time compilation]] (JIT), a DBT technique also used by dynarmic that makes Unicorn a sufficiently performant framework for Tegra X1 emulation. It is based on [https://www.qemu.org QEMU], a widely-used generic machine emulator framework that achieves near-native performance in many scenarios.</div></td></tr> <tr><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><br></td><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><br></td></tr> <tr><td class="diff-marker" data-marker="−"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>AArch64 implements privilege as [https://developer.arm.com/documentation/102412/0103/Privilege-and-Exception-levels/Exception-levels Exception <del style="font-weight: bold; text-decoration: none;">levels</del>] (ELs) numbered <code>EL0</code> through <code>EL3</code>. In this exception model, exceptions may only be raised to an EL identical to that of the caller, and may only be returned from to an EL lower than that of the callee. The NX mostly follows the typical AArch64 EL software model in which userland code runs at <code>EL0</code>, the OS at <code>EL1</code>, the hypervisor at <code>EL2</code>, and the [https://developer.arm.com/documentation/100935/0100/Switching-betwen-the-Normal-and-Secure-worlds- Secure Monitor] at <code>EL3</code>, though the NX lacks a hypervisor, so exceptions raised by <code>EL1</code> are taken directly to <code>EL3</code>. Because jabara emulates HOS itself, its implementation of HOS functionality can be thought of as <code>EL1</code> code—however, as this code is entirely invisible to the guest system, it is not actually running at any EL. Exceptions raised to <code>EL1</code> must hence be handled by jabara, and higher ELs—of which only <code>EL3</code> is used by the NX—can be ignored.</div></td><td class="diff-marker" data-marker="+"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>AArch64 implements privilege as [https://developer.arm.com/documentation/102412/0103/Privilege-and-Exception-levels/Exception-levels Exception <ins style="font-weight: bold; text-decoration: none;">Levels</ins>] (ELs) numbered <code>EL0</code> through <code>EL3</code>. In this exception model, exceptions may only be raised to an EL identical to <ins style="font-weight: bold; text-decoration: none;">or higher than </ins>that of the caller, and may only be returned from to an EL lower than that of the callee. The NX mostly follows the typical AArch64 EL software model in which userland code runs at <code>EL0</code>, the OS at <code>EL1</code>, the hypervisor at <code>EL2</code>, and the [https://developer.arm.com/documentation/100935/0100/Switching-betwen-the-Normal-and-Secure-worlds- Secure Monitor] at <code>EL3</code>, though the NX lacks a hypervisor, so exceptions raised by <code>EL1</code> are taken directly to <code>EL3</code>. Because jabara emulates HOS itself, its implementation of HOS functionality can be thought of as <code>EL1</code> code—however, as this code is entirely invisible to the guest system, it is not actually running at any EL. Exceptions raised to <code>EL1</code> must hence be handled by jabara, and higher ELs—of which only <code>EL3</code> is used by the NX—can be ignored.</div></td></tr> <tr><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><br></td><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><br></td></tr> <tr><td class="diff-marker" data-marker="−"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>In AArch64, SVCs are implemented as exceptions raised to <code>EL1</code> by the <code>[https://developer.arm.com/documentation/111182/2025-09_ASL1/Base-Instructions/SVC--Supervisor-call-?lang=en SVC]</code> ("supervisor call") A64 instruction. As raising execution to <code>EL1</code> is required for userland (<code>EL0</code>) applications to call kernel (<code>EL1</code>) functionality, SVCs are used for all userland calls to kernel code, and hence must be implemented in jabara in order to run userland NX applications. The Rust bindings for Unicorn expose <code>[https://docs.rs/unicorn-engine/latest/unicorn_engine/struct.Unicorn.html#method.add_intr_hook Unicorn<'a, D>::add_intr_hook]</code>, which hooks guest interrupts and exceptions, passing a <code>u32</code> interrupt code to the hook function. The interrupt codes are defined in <code>[https://git.zelda.sr/jabara/unicorn/src/commit/3811fdcb861dc7686dde0ec0a7624bb92e277647/qemu/target/arm/cpu.h#L32-L52 qemu/target/arm/cpu.h]</code>, with <code>EXCP_SWI</code> ('''s'''oft'''w'''are '''i'''nterrupt) being the code used for guest exceptions. If a caught interrupt is a software interrupt, the details of the exception raised are available via the Exception Syndrome Register for the current <del style="font-weight: bold; text-decoration: none;">Exception level</del>; for <code>SVC</code> exceptions, this is <code>EL1</code>, so the <code>[https://developer.arm.com/documentation/111180/2025-09_ASL1/AArch64-Registers/ESR-EL1--Exception-Syndrome-Register--EL1-?lang=en ESR_EL1]</code> (Exception Syndrome Register (EL1)) register must be read. <code>SVC</code> exceptions can be identified by an <code>[https://developer.arm.com/documentation/111180/2025-09_ASL1/AArch64-Registers/ESR-EL1--Exception-Syndrome-Register--EL1-?lang=en#fieldset_0-31_26 EC]</code> (Exception Class) value of <code>0b010101</code> ("<code>SVC</code> instruction execution in AArch64 state"), located at bits <code>26</code> through <code>31</code>, and an <code>[https://developer.arm.com/documentation/111180/2025-09_ASL1/AArch64-Registers/ESR-EL1--Exception-Syndrome-Register--EL1-?lang=en#fieldset_0-25_25 IL]</code> (Instruction Length) value of <code>0b1</code> ("32-bit instruction trapped"), located at bit <code>25</code>. The immediate argument, <code>[https://developer.arm.com/documentation/111182/2025-09_ASL1/Base-Instructions/SVC--Supervisor-call-?lang=en#imm imm16]</code>, of a caught <code>SVC</code> exception is encoded in the <code>[https://developer.arm.com/documentation/111180/2025-09_ASL1/AArch64-Registers/ESR-EL1--Exception-Syndrome-Register--EL1-?lang=en#fieldset_0-24_0_11 ISS]</code> (Instruction Specific Syndrome) field, located at bits <code>0</code> through <code>15</code>. <code>imm16</code> is then used to uniquely identify the called SVC, allowing the correct SVC implementation in jabara to be called. Exception Syndrome Registers are not exposed by Unicorn's AArch64 API, so Unicorn was forked to [https://git.zelda.sr/jabara/unicorn jabara/unicorn] to add this functionality, exposing an <code>ESR</code> read-only pseudoregister that accesses the Exception Syndrome Register for the current <del style="font-weight: bold; text-decoration: none;">Exception level</del>, always <code>EL1</code> in jabara. This allows SVCs to be implemented per immediate (<code>imm16</code>) in native Rust code, callable by the guest machine with the <code>SVC</code> instruction.</div></td><td class="diff-marker" data-marker="+"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>In AArch64, SVCs are implemented as exceptions raised to <code>EL1</code> by the <code>[https://developer.arm.com/documentation/111182/2025-09_ASL1/Base-Instructions/SVC--Supervisor-call-?lang=en SVC]</code> ("supervisor call") A64 instruction. As raising execution to <code>EL1</code> is required for userland (<code>EL0</code>) applications to call kernel (<code>EL1</code>) functionality, SVCs are used for all userland calls to kernel code, and hence must be implemented in jabara in order to run userland NX applications. The Rust bindings for Unicorn expose <code>[https://docs.rs/unicorn-engine/latest/unicorn_engine/struct.Unicorn.html#method.add_intr_hook Unicorn<'a, D>::add_intr_hook]</code>, which hooks guest interrupts and exceptions, passing a <code>u32</code> interrupt code to the hook function. The interrupt codes are defined in <code>[https://git.zelda.sr/jabara/unicorn/src/commit/3811fdcb861dc7686dde0ec0a7624bb92e277647/qemu/target/arm/cpu.h#L32-L52 qemu/target/arm/cpu.h]</code>, with <code>EXCP_SWI</code> ('''s'''oft'''w'''are '''i'''nterrupt) being the code used for guest exceptions. If a caught interrupt is a software interrupt, the details of the exception raised are available via the Exception Syndrome Register for the current <ins style="font-weight: bold; text-decoration: none;">EL</ins>; for <code>SVC</code> exceptions, this is <code>EL1</code>, so the <code>[https://developer.arm.com/documentation/111180/2025-09_ASL1/AArch64-Registers/ESR-EL1--Exception-Syndrome-Register--EL1-?lang=en ESR_EL1]</code> (Exception Syndrome Register (EL1)) register must be read. <code>SVC</code> exceptions can be identified by an <code>[https://developer.arm.com/documentation/111180/2025-09_ASL1/AArch64-Registers/ESR-EL1--Exception-Syndrome-Register--EL1-?lang=en#fieldset_0-31_26 EC]</code> (Exception Class) value of <code>0b010101</code> ("<code>SVC</code> instruction execution in AArch64 state"), located at bits <code>26</code> through <code>31</code>, and an <code>[https://developer.arm.com/documentation/111180/2025-09_ASL1/AArch64-Registers/ESR-EL1--Exception-Syndrome-Register--EL1-?lang=en#fieldset_0-25_25 IL]</code> (Instruction Length) value of <code>0b1</code> ("32-bit instruction trapped"), located at bit <code>25</code>. The immediate argument, <code>[https://developer.arm.com/documentation/111182/2025-09_ASL1/Base-Instructions/SVC--Supervisor-call-?lang=en#imm imm16]</code>, of a caught <code>SVC</code> exception is encoded in the <code>[https://developer.arm.com/documentation/111180/2025-09_ASL1/AArch64-Registers/ESR-EL1--Exception-Syndrome-Register--EL1-?lang=en#fieldset_0-24_0_11 ISS]</code> (Instruction Specific Syndrome) field, located at bits <code>0</code> through <code>15</code>. <code>imm16</code> is then used to uniquely identify the called SVC, allowing the correct SVC implementation in jabara to be called. Exception Syndrome Registers are not exposed by Unicorn's AArch64 API, so Unicorn was forked to [https://git.zelda.sr/jabara/unicorn jabara/unicorn] to add this functionality, exposing an <code>ESR</code> read-only pseudoregister that accesses the Exception Syndrome Register for the current <ins style="font-weight: bold; text-decoration: none;">EL</ins>, always <code>EL1</code> in jabara. This allows SVCs to be implemented per immediate (<code>imm16</code>) in native Rust code, callable by the guest machine with the <code>SVC</code> instruction.</div></td></tr> <tr><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><br></td><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><br></td></tr> <tr><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>== Notes ==</div></td><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>== Notes ==</div></td></tr>  </table> Mon, 13 Jul 2026 11:45:24 GMT Mako https://wiki.zelda.sr/wiki/Talk:Design